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SEMICONDUCTOR DEVICE WITH LOW-RESISTANCE INLAID COPPER/BARRIER INTERCONNECTS AND METHOD FOR MANUFACTURING THE SAME

机译:具有低电阻倾斜铜/栅栏互连的半导体器件及其制造方法

摘要

An inlaid copper/barrier interconnect includes a semiconductor substrate; a carbon-doped oxide (CDO) dielectric layer disposed over the semiconductor substrate; a damascene recess etched into the CDO dielectric layer; an alpha-phase tantalum (α-Ta) single-layer barrier sputter deposited on sidewall and bottom of the damascene recess; and a conductive layer deposited directly on the alpha-phase tantalum single-layer barrier, wherein the conductive layer fills the damascene recess. According to one preferred embodiment, the alpha-phase tantalum single-layer barrier has a resistivity of about 25 μΩ-cm.
机译:镶嵌铜/势垒互连包括:半导体衬底;碳掺杂氧化物(CDO)介电层设置在半导体衬底上方;刻蚀到CDO介电层中的镶嵌凹槽;沉积在镶嵌凹槽的侧壁和底部的α相钽(α-Ta)单层势垒溅射;导电层直接沉积在α相钽单层势垒上,其中该导电层填充镶嵌凹陷。根据一个优选实施例,α相钽单层势垒具有约25μΩ-cm的电阻率。

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