INTEGRATED CIRCUIT FABRICATION USING SOLID PHASE EPITAXY AND SILICON ON INSULATOR TECHNOLOGY

摘要

A method of forming a junction extension in respect of a CMOS device based on a composite semiconductor-on-insulator substrate (50). The method comprises performing an implementation step to form a buried amorphous layer (56) in the semiconductor layer (52) of the substrate, such that a portion of the crystalline semiconductor layer (52) is left covering the buried layer (56). A doping step is performed to create a doped region (58) in the semiconductor layer (52). The structure is then annealed at a relatively low temperature so as to cause re-crystallization of the semiconductor layer (52) and activation of the dopants forming the doped region (58).