首页> 外国专利> SIMULATION OF DESIGNS USING RE-CONFIGURABLE LOGIC

SIMULATION OF DESIGNS USING RE-CONFIGURABLE LOGIC

机译:使用可重构逻辑对设计进行仿真

摘要

A means of increasing the steady-state simulation speed of a design comprising digital, analog, mixed-signal and full-wave components is taught using general purpose processors and electronically re-configurable logic. The innovative compilation and execution method disclosed uses either a single compilation step before the onset of simulation or incremental compilation during simulation to yield multiple, optimized processor instructions, logic configurations and interconnect configurations specific to the operating contexts encountered during execution embedded within a pseudo-static execution schedule. Caching provides for rapid re-use of compilation results specific to an operating context. Key innovative steps embodied in the apparatus include use of to represent time-varying changes in design state rather than the actual value of design state at each time point, encapsulation of component model functionality, dynamically varying numerical range in hardware, and integration of a reduced latency interconnect in close proximity to the acceleration resources.
机译:使用通用处理器和电子可重配置逻辑来教导提高包含数字,模拟,混合信号和全波组件的设计的稳态仿真速度的方法。所公开的创新的编译和执行方法在仿真开始之前使用单个编译步骤,或者在仿真期间使用增量编译来产生多个优化的处理器指令,逻辑配置和互连配置,这些特定于执行期间所遇到的操作上下文的伪静态嵌入嵌入式静态环境中执行时间表。缓存可以快速重用特定于操作上下文的编译结果。设备中体现的关键创新步骤包括:使用代表每个时间点设计状态的时变变化,而不是设计状态的实际值;封装组件模型功能;动态改变硬件中的数值范围;以及集成精简版延迟互连紧密靠近加速资源。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号