首页> 外国专利> INTEGRATED CIRCUIT COMPRISING LATERALLY DIELECTRICALLY ISOLATED ACTIVE REGIONS ABOVE AN ELECTRICALLY CONTACTED BURIED MATERIAL, AND METHOD FOR PRODUCING THE SAME

INTEGRATED CIRCUIT COMPRISING LATERALLY DIELECTRICALLY ISOLATED ACTIVE REGIONS ABOVE AN ELECTRICALLY CONTACTED BURIED MATERIAL, AND METHOD FOR PRODUCING THE SAME

机译:包含在电绝缘材料上方的横向介电隔离有源区域的集成电路及其制造方法

摘要

The invention relates to an integrated circuit comprising a first layer (12) consisting of an active semiconductor material extending along a first side (14) of a buried layer (16), and trench structures (18, 38) that cut through the layer (12) of active semiconductor material and have dielectric wall regions (42, 44). Said dielectric wall regions (42, 44) electrically isolate partial regions (52, 54, 56) of the layer (12) of active semiconductor material in the lateral direction, and the trench structures (18, 38) also comprise first inner regions (46) that are filled with an electroconductive material and electroconductively contact the buried layer (16). The integrated circuit is characterised in that first wall regions (42) of the trench structures (18, 38) completely cut through the buried layer (16), and second wall regions (44) of the trench structures (18, 38) protrude into the buried layer (16), without completely cutting the same. The invention also relates to a method for producing one such integrated circuit.
机译:本发明涉及一种集成电路,其包括:第一层(12),其由沿着掩埋层(16)的第一侧(14)延伸的活性半导体材料;以及沟槽结构(18、38),其穿过该层(有源半导体材料具有如图12所示的结构并且具有介电壁区域(42、44)。所述介电壁区域(42、44)在横向方向上将有源半导体材料层(12)的部分区域(52、54、56)电隔离,并且沟槽结构(18、38)也包括第一内部区域( 46)中填充有导电材料并与掩埋层(16)导电接触。该集成电路的特征在于,沟槽结构(18、38)的第一壁区域(42)完全切穿掩埋层(16),并且沟槽结构(18、38)的第二壁区域(44)突出到掩埋层(16),而无需完全切割。本发明还涉及一种用于生产这样的集成电路的方法。

著录项

  • 公开/公告号EP1706901A1

    专利类型

  • 公开/公告日2006-10-04

    原文格式PDF

  • 申请/专利权人 ATMEL GERMANY GMBH;

    申请/专利号EP20050706945

  • 发明设计人 DUDEK VOLKER;

    申请日2005-01-21

  • 分类号H01L21/74;H01L21/62;

  • 国家 EP

  • 入库时间 2022-08-21 21:26:35

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