首页> 外国专利> AN ADIABATIC LOGIC CIRCUIT FOR ULTRA LOW POWER CIRCUIT DESIGN

AN ADIABATIC LOGIC CIRCUIT FOR ULTRA LOW POWER CIRCUIT DESIGN

机译:用于超低功耗电路设计的绝热逻辑电路

摘要

present invention can effectively reduce the energy loss in ultra-low-power circuit design for an adiabatic logic circuits offer that, 90 receiving sequentially one of a plurality of clocks having a phase difference of voltage operations and, in a first channel transistor having a threshold voltage and a second low-power logic circuit having a heat insulating transistor having a second channel threshold voltage , receive input a second input and a first input for receiving the first output terminal and a second output terminal, and the pass transistor to pass a portion of the clock voltage is one of the input if the input is high level, the output terminal of the output signals and a path control unit that controls the path of the transistor output stage and ground, when the clock voltage exceeds the threshold voltage of the first channel turn-on of the output against the high level is inputted through said input path control transistor When the ground, and the clock voltage exceeds the threshold voltage of the second channel cross-coupled to output the energy put through the pass transistor to the output node corresponding to the input latch and the time of the fall of the clock voltage is at the ground the energy output by the latch portion of the cross-coupling features a switching transistor to restore the energy return portion yirueojim the clock voltage.
机译:本发明可以有效地减少绝热逻辑电路的超低功率电路设计中的能量损失,该设计提供了:90顺序地接收具有电压操作的相位差的多个时钟之一,并且在具有阈值的第一沟道晶体管中。电压和具有绝缘晶体管的第二低功率逻辑电路,该绝缘晶体管具有第二沟道阈值电压,接收输入,第二输入和第一输入以接收第一输出端子和第二输出端子,以及通过晶体管以使一部分通过如果输入电压为高电平,则时钟电压的一个是输入之一,输出信号的输出端,以及一个路径控制单元,当时钟电压超过该阈值电压的阈值电压时,该路径控制单元控制晶体管输出级和地的路径当接地且时钟电压超过t时,通过所述输入路径控制晶体管输入针对高电平的输出的第一通道导通第二通道的阈值电压交叉耦合,以将通过传输晶体管的能量输出到与输入锁存器相对应的输出节点,并且时钟电压下降的时间为地时,由锁存器部分输出的能量交叉耦合具有开关晶体管,以恢复时钟回路电压的能量返回部分。

著录项

  • 公开/公告号KR20060059596A

    专利类型

  • 公开/公告日2006-06-02

    原文格式PDF

  • 申请/专利权人 INHA-INDUSTRY PARTNERSHIP INSTITUTE;

    申请/专利号KR20040098725

  • 发明设计人 KANG JIN KU;

    申请日2004-11-29

  • 分类号H03K19;

  • 国家 KR

  • 入库时间 2022-08-21 21:25:36

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