Electrically erasable PROM cell for silicon chip, has transistor to control injection/extraction of electric charges into floating gate by applying electric potential for erasing/programming of cell on drain region of transistor

摘要

The cell has a floating gate transistor (FGTE) with a tunnel window (TW) arranged between an end part (43-3) of a floating gate (43) and a source region (51) of a control transistor (CT) for injection/extraction of electric charges into the gate. The transistor (CT) controls injection/extraction by applying an electric potential for erasing/programming the cell on a drain region (50) of the transistor (CT), in a programming phase. An independent claim is also included for a memory plane comprising memory cells.