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IMPURITY ANALYSIS METHOD, AND IMPURITY ANALYSIS JIG OF SEMICONDUCTOR SUBSTRATE

机译:杂质分析方法以及半导体基板的杂质分析夹具

摘要

PROBLEM TO BE SOLVED: To provide an impurity analysis method and an impurity analysis jig of a semiconductor substrate having a sufficient accuracy.;SOLUTION: A main surface of a semiconductor substrate is masked with a protective plate having an opening in a central part, the etching liquid is spread in the opening of the protective plate, and the method comprises: a first step (S01 to S04) of etching a surface layer of the semiconductor substrate; a second step (S05 to S06) of analyzing impurity in the surface layer of the semiconductor substrate; and a third step (S07 to S10) of sandwiching the etching liquid between gaps and etching a non-etched area of the surface layer of the semiconductor substrate, wherein the first to third steps are repeated for a prescribed number of times (S11). Contamination from the non-etched area of the surface layer of the semiconductor substrate is prevented to perform impurity analysis.;COPYRIGHT: (C)2007,JPO&INPIT
机译:解决的问题:提供一种具有足够精度的半导体衬底的杂质分析方法和杂质分析夹具。解决方案:半导体衬底的主表面被在中央部分具有开口的保护板遮盖,蚀刻液散布在保护板的开口中,该方法包括:蚀刻半导体衬底的表面层的第一步骤(S01至S04);第二步骤(S05至S06),用于分析半导体衬底的表面层中的杂质;第三步骤(S07至S10),其将蚀刻液夹在间隙之间并蚀刻半导体基板的表面层的未蚀刻区域,其中,将第一至第三步骤重复规定次数(S11)。防止半导体衬底表面层未蚀刻区域的污染进行杂质分析。;版权所有:(C)2007,JPO&INPIT

著录项

  • 公开/公告号JP2007208198A

    专利类型

  • 公开/公告日2007-08-16

    原文格式PDF

  • 申请/专利权人 TOSHIBA CORP;

    申请/专利号JP20060028643

  • 发明设计人 MIZUNO AYAKO;UOZUMI NOBUHIRO;

    申请日2006-02-06

  • 分类号H01L21/66;

  • 国家 JP

  • 入库时间 2022-08-21 21:15:28

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