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Duty-cycle correction circuit for differential clocking

机译:差分时钟的占空比校正电路

摘要

A completely differential approach to correcting duty-cycle distortions of a differential clock signal propagating through a differential amplifier. A duty-cycle distortion correction (DCDC) differential amplifier circuit/device is provided with a differential amplifier whose output wires are coupled to a correction circuit. The correction circuit comprises a differential low pass filter and a differential correction amplifier. The differential correction amplifier's output is dotted back into the output of the amplifier. The differential output of the amplifier is passed through the low pass filter, which provides differential DC output signals that triggers respective correction amplifier transistors to generate an inverted correction current that is added back to respective differential output pulse. The DCDC differential amplifier provides a completely differential approach to correction of duty-cycle distortions within the differential output.
机译:一种完全差分方法,用于校正通过差分放大器传播的差分时钟信号的占空比失真。占空比失真校正(DCDC)差分放大器电路/装置设有差分放大器,其输出线耦合至校正电路。校正电路包括差分低通滤波器和差分校正放大器。差分校正放大器的输出点回到放大器的输出中。放大器的差分输出通过低通滤波器,该低通滤波器提供差分DC输出信号,该信号会触发相应的校正放大器晶体管以生成反相的校正电流,该反相的校正电流会加回到相应的差分输出脉冲上。 DCDC差分放大器提供了一种完全差分方法来校正差分输出中的占空比失真。

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