首页> 外国专利> Method and apparatus employing integrated metrology for improved dielectric etch efficiency

Method and apparatus employing integrated metrology for improved dielectric etch efficiency

机译:采用集成计量技术以提高介电蚀刻效率的方法和设备

摘要

A method and apparatus for processing a semiconductor wafer is provided for reducing dimensional variation by feeding forward information relating to photoresist mask CD and profile and underlying layer thickness measured at several points on the wafer to adjust the next process the inspected wafer will undergo (e.g., the etch process). After the processing step, dimensions of a structure formed by the process, such as the CD and depth of a trench formed by the process, are measured at several points on the wafer, and this information is fed back to the process tool to adjust the process for the next wafer to further reduce dimensional variation. In certain embodiments, the CD, profile, thickness and depth measurements, etch processing and post-etch cleaning are performed at a single module in a controlled environment. All of the transfer and processing steps performed by the module are performed in a clean environment, thereby increasing yield by avoiding exposing the wafer to the atmosphere and possible contamination between steps.
机译:提供了一种用于处理半导体晶片的方法和设备,用于通过前馈与光致抗蚀剂掩模CD以及在晶片上的几个点处测量的轮廓和下层厚度有关的信息,以调整尺寸,以调整被检查晶片将经历的下一工序(例如,蚀刻工艺)。在处理步骤之后,在晶片上的几个点处测量由该过程形成的结构的尺寸,例如CD和由该过程形成的沟槽的深度,并将该信息反馈给处理工具以调整晶片的尺寸。下一晶片的工艺进一步减小尺寸变化。在某些实施例中,CD,轮廓,厚度和深度测量,蚀刻处理和蚀刻后清洁在受控环境中的单个模块上执行。由模块执行的所有转移和处理步骤均在清洁的环境中进行,从而避免了将晶片暴露于大气以及步骤之间可能的污染,从而提高了产量。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号