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Methods and apparatus for signal modification in a fractional-N phase locked loop system

机译:在分数N锁相环系统中进行信号修改的方法和装置

摘要

A phase locked loop includes a buffer that synchronizes the transmission of the new count value to the completion of the previous count to avoid errors caused by dithering. The buffer is connected to a count input of the counter and transmits the new count upon receipt of the carryout signal from the counter. Alternatively, the transmission of the new value of N from the buffer is delayed after receipt by the buffer of a carryout signal from the counter. In another embodiment, a delayed version of the carryout signal is used to trigger the buffer to transmit the new count value to the counter. In another feature, a buffer synchronizes phase data to a reference signal before inputting it to a digital modulator of the phase locked loop.
机译:锁相环包括一个缓冲区,该缓冲区将新计数值的传输与先前计数的完成同步,以避免抖动引起的错误。缓冲器连接到计数器的计数输入,并在从计数器接收到进位信号时发送新的计数。可替代地,在缓冲器接收到来自计数器的进位信号之后,延迟从缓冲器发送新的N值。在另一个实施例中,进位信号的延迟版本用于触发缓冲器以将新的计数值发送到计数器。在另一个特征中,缓冲器在将相位数据输入到锁相环的数字调制器之前将其同步到参考信号。

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