TWIN EEPROM MEMORY TRANSISTORS WITH SUBSURFACE STEPPED FLOATING GATES

摘要

A memory array (10) with memory cells (13) arranged in rows and columns with each cell having twin EEPROMs (15, 115) featuring subsurface stepped (53, 54) floating gates for electric field concentration. The twin EEPROMs employ only a single layer of poly, one portion being a floating gate (82, 84) of each EEPROM and another portion being word lines (WL1, WL2). The twin EEPROMs share a common subsurface electrode (92) by having diffused control lines (62, 64) and a diffused bit line (BL1). The EEPROMs are symmetric across the common electrode.