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NOR Flash Memory Array and Operating Method of the same Using Charge Trap Memory Cell with Multi-Doped Layers

机译:使用具有多掺杂层的电荷陷阱存储单元的NOR闪存阵列及其操作方法

摘要

The present invention relates to a NOR flash memory array using a charge trap memory cell having a plurality of doped layers in an active region and a method of operating the same.;Unlike the structure of the conventional charge trap memory cell, the memory cell used in the present invention appropriately forms a plurality of doping layers in the active region, thereby inducing electrons to be band-band tunneled at the portion forming the PN junction with the source / drain region, The electrons are accelerated in a predetermined reverse bias state to induce an avalanche phenomenon, and the holes generated at this time are injected into the charge trap layers of each charge trap memory cell. The method provides a method of operating a NOR flash memory array by injecting N into a charge trap layer of each cell.;Charge Trap, Flash Memory, Tunneling, Avalanche, NOR
机译:本发明涉及一种使用在有源区中具有多个掺杂层的电荷陷阱存储单元的NOR闪存阵列及其操作方法。与传统电荷陷阱存储单元的结构不同,所使用的存储单元在本发明中,在有源区中适当地形成多个掺杂层,从而诱导电子在与源/漏区形成PN结的部分处以带状隧穿,电子以预定的反向偏置状态被加速至引起雪崩现象,并且此时产生的空穴被注入到每个电荷陷阱存储单元的电荷陷阱层中。该方法提供了一种通过将N注入每个单元的电荷陷阱层来操作NOR闪存阵列的方法。电荷陷阱,闪存,隧道,雪崩,NOR

著录项

  • 公开/公告号KR100663977B1

    专利类型

  • 公开/公告日2007-01-02

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20050009846

  • 发明设计人 심재성;박병국;이종덕;김정우;

    申请日2005-02-03

  • 分类号H01L27/115;H01L21/314;

  • 国家 KR

  • 入库时间 2022-08-21 20:33:17

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