首页> 外国专利> LEVEL SHIFT CIRCUIT FOR STEPPING UP LOGIC SIGNAL AMPLITUDE WITH IMPROVED OPERATING SPEED

LEVEL SHIFT CIRCUIT FOR STEPPING UP LOGIC SIGNAL AMPLITUDE WITH IMPROVED OPERATING SPEED

机译:用于提高逻辑信号幅度并提高操作速度的电平转换电路

摘要

is an object of the present invention is to provide a level shift circuit that operates at a higher speed . ; VDD1 & between VDD2 of the power source potential (VDD2) and the reference potential (VSS) PMOS transistors constituting the first inverter is connected between (P1) and an NMOS transistor (N1S), also an NMOS transistor (N3 and NS3) are connected in series , and between the PMOS transistors constituting the second inverter in the same way (P2) and the NMOS transistor (N2S), is also an NMOS transistor (N4 and N4S) are connected in series . A gate insulating film of the PMOS transistor (P1, P2) and an NMOS transistor (N3 and N4) is thicker than the gate insulating film of the NMOS transistor (N1S~N4S). The gate of the NMOS transistor (N3 and N4) is connected to the VDD2, the gate of the NMOS transistor (N3S and N4S) is connected to the VDD1, the transistors are always turned on .
机译:本发明的一个目的是提供一种以较高速度工作的电平移位电路。 ; VDD1&构成第一反相器的电源电位(VDD2)的VDD2和基准电位(VSS)之间连接在(P1)和NMOS晶体管(N1S)之间,并且NMOS晶体管(N3和NS3)串联连接并且,在以相同方式构成第二反相器的PMOS晶体管(P2)和NMOS晶体管(N2S)之间,也串联连接有NMOS晶体管(N4和N4S)。 PMOS晶体管(P1,P2)和NMOS晶体管(N3和N4)的栅极绝缘膜比NMOS晶体管(N1S〜N4S)的栅极绝缘膜厚。 NMOS晶体管(N3和N4)的栅极连接到VDD2,NMOS晶体管(N3S和N4S)的栅极连接到VDD1,晶体管始终导通。

著录项

  • 公开/公告号KR100757283B1

    专利类型

  • 公开/公告日2007-09-11

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20010075297

  • 发明设计人 야마구치세이이치로;

    申请日2001-11-30

  • 分类号H03K19/0175;

  • 国家 KR

  • 入库时间 2022-08-21 20:31:22

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号