Level shift circuit for stepping up logic signal amplitude with improved operating speed

摘要

NMOS transistors N3 and N3S are connected in series between a PMOS transistor P1 and an NMOS transistor N1S constituting a first inverter connected between a power supply potential VDD2, which satisfies VDD1VDD2, and a ground potential VSS, and likewise, NMOS transistors N4 and N4S are connected in series between a PMOS transistor P2 and an NMOS transistor N2S constituting a second inverter. The gate insulating films of the MOS transistors P1, P2, N3 and N4 are thicker than those of the transistors N1S and N4S. The gates of the NMOS transistors N3 and N4 are connected to VDD2, the gates of NMOS transistors N3S and N4S are connected to VDD1 and these transistors are constantly on.