首页> 外国专利> MOS TRANSISTOR, METHOD FOR MANUFACTURING THE SAME MOS TRANSISTOR, CMOS TYPE SEMICONDUCTOR DEVICE USING THE SAME MOS TRANSISTOR, AND SEMICONDUCTOR DEVICE USING THE SAME CMOS TYPE SEMICONDUCTOR DEVICE

MOS TRANSISTOR, METHOD FOR MANUFACTURING THE SAME MOS TRANSISTOR, CMOS TYPE SEMICONDUCTOR DEVICE USING THE SAME MOS TRANSISTOR, AND SEMICONDUCTOR DEVICE USING THE SAME CMOS TYPE SEMICONDUCTOR DEVICE

机译:MOS晶体管,制造相同MOS晶体管的方法,使用相同MOS晶体管的CMOS型半导体器件以及使用相同CMOS型半导体器件的半导体器件

摘要

PROBLEM TO BE SOLVED: To provide an MOS transistor in which a stressor is arranged so that a stress to be generated by a stressor can be much more efficiently applied to the channel part of the MOS transistor and a method for manufacturing the MOS transistor and a CMOS type semiconductor device using the MOS transistor.;SOLUTION: The MOS transistor includes: a silicon substrate; a gate insulating film on the silicon substrate; a gate electrode on the gate insulating film; source/drain regions formed at the both sides of the gate electrode; a region isolated from the surface of the silicon substrate, and interposed between the source/drain regions, that is, a stress generation substrate embedded region formed in the silicon substrate at the lower part of the gate electrode, and embedded with stress generation substance. A method for manufacturing the MOS transistor and a CMOS type semiconductor device using the MOS transistor are provided.;COPYRIGHT: (C)2008,JPO&INPIT
机译:解决的问题:提供一种MOS晶体管,该晶体管中布置有应力源,以便可以将由应力源产生的应力更有效地施加到该MOS晶体管的沟道部分,以及该MOS晶体管的制造方法和使用该MOS晶体管的CMOS型半导体器件。硅基板上的栅极绝缘膜;栅绝缘膜上的栅电极;在栅电极的两侧形成源/漏区;与硅衬底的表面隔离并且插入在源极/漏极区域之间的区域,即在栅电极下部的硅衬底中形成的并且应力产生物质被埋入的应力产生衬底嵌入区域。提供了一种制造MOS晶体管的方法和使用该MOS晶体管的CMOS型半导体器件。;版权所有:(C)2008,日本特许厅&INPIT

著录项

  • 公开/公告号JP2008153515A

    专利类型

  • 公开/公告日2008-07-03

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP20060341318

  • 发明设计人 IKEDA KEIJI;MIYASHITA TOSHIHIKO;

    申请日2006-12-19

  • 分类号H01L29/78;H01L21/8238;H01L27/092;H01L21/336;

  • 国家 JP

  • 入库时间 2022-08-21 20:24:15

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