Ultra low power SRAM cell design

摘要

A semiconductor SRAM cell is provided and includes two back-to-back inverters and two p-channel (PMOS) access transistors. In one preferred embodiment the sources of two pull down n-channel (NMOS) transistors are connected to the drain of the ground NMOS transistor, which is connected to ground. During write operation the ground transistor is turned off and the sources of the pull down transistors are floating with high impedance. The precharge circuit is still active and both bit lines are driven “high” with low impedance. The PMOS access transistors are turned on. The two cell nodes are precharged “high.” The precharge cycle is deactivated and the write circuit is activated to transfer a small voltage difference between the bit lines, which is transferred to the cell nodes. Then the access transistors are turned off and the ground transistor is activated to amplify the small voltage difference on the cell nodes.