首页> 外国专利> METHOD FOR REALIZING A CONTACT OF AN INTEGRATED WELL IN A SEMICONDUCTOR SUBSTRATE, IN PARTICULAR FOR A BASE TERMINAL OF A BIPOLAR TRANSISTOR, WITH ENHANCEMENT OF THE TRANSISTOR PERFORMANCES

METHOD FOR REALIZING A CONTACT OF AN INTEGRATED WELL IN A SEMICONDUCTOR SUBSTRATE, IN PARTICULAR FOR A BASE TERMINAL OF A BIPOLAR TRANSISTOR, WITH ENHANCEMENT OF THE TRANSISTOR PERFORMANCES

机译:实现半导体基体中集成阱接触的方法,特别是对于双极晶体管的基础端子,通过增强晶体管性能来实现

摘要

A method realizes a contact of a first well of a first type of dopant integrated in a semiconductor substrate next to a second well of a second type of dopant and forming with it a parasitic diode. The method comprises: formation of the first well; formation of the second well next to the first well; definition of an oxide layer above the first and second wells; and formation of an electric contact layer above the oxide layer in correspondence with the first well for realizing an electric contact with it. The definition step of the oxide layer further comprises a deposition step of this oxide layer above the whole first well and a removal step of at least one portion of the oxide layer in correspondence with a contact area of the first well so that the contact area has a shorter length than a length of the first well.
机译:一种方法实现了集成在半导体衬底中的第一类型掺杂剂的第一阱与第二类型掺杂剂的第二阱相邻的接触,并与之形成寄生二极管。该方法包括:第一井的形成;在第一口井旁边形成第二口井;在第一和第二阱上方的氧化物层的定义;对应于第一阱,在氧化物层上方形成电接触层,以实现与之的电接触。氧化物层的限定步骤还包括在整个第一阱上方的该氧化物层的沉积步骤以及与第一阱的接触面积相对应的氧化物层的至少一部分的去除步骤,使得该接触面积具有比第一孔的长度短。

著录项

  • 公开/公告号US2008246118A1

    专利类型

  • 公开/公告日2008-10-09

    原文格式PDF

  • 申请/专利权人 VINCENZO ENEA;CESARE RONSISVALLE;

    申请/专利号US20080039610

  • 发明设计人 CESARE RONSISVALLE;VINCENZO ENEA;

    申请日2008-02-28

  • 分类号H01L29/73;H01L21/22;

  • 国家 US

  • 入库时间 2022-08-21 20:12:42

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