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Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices
Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices
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机译:用于高性能混合取向绝缘体上硅CMOS器件的混合衬底的结构和制造方法
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摘要
The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of a planar hybrid substrate. The method of the present invention also improves the performance of creating SOI-like devices with a combination of a buried insulator and counter-doping layers. The present invention also relates to semiconductor structures that are formed utilizing the method of the present invention.
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