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a flexible printed circuit board having flip chip bonding domain aligned top layer bump and inner layer trace

机译:柔性印刷电路板,具有倒装芯片键合域对齐的顶层凸点和内层走线

摘要

A flexible printed circuit board having a flip chip bonding region on which a top layer bump and an inner layer trace is provided to optimize a space use by forming the inner layer trace wider than a width of the top layer bump. A flexible printed circuit board having a flip chip bonding region on which a top layer bump and an inner layer trace includes a flip chip bonding region(10), the top layer bump(13), and the inner layer trace(11). The top layer bump(13) and the inner layer trace(11) are formed to be overlapped on the flip chip bonding region. The width of the top layer bump(13) is formed wider than the width of the inner layer trace(11). The width of the inner layer trace(11) is wider as much as 5~20 % than the width of the top layer bump. The correlation of the width of the inner layer trace(11) and the width of the top layer bump(13) is adapted to the flexible printed circuit board having at least two layers.
机译:提供一种具有倒装芯片接合区域的柔性印刷电路板,在该倒装芯片接合区域上,顶层凸块和内层迹线通过形成比顶层凸块的宽度宽的内层迹线来优化空间使用。一种具有倒装芯片接合区域的柔性印刷电路板,在该倒装芯片接合区域上,顶层凸块和内层迹线包括倒装芯片接合区域(10),顶层凸块(13)和内层迹线(11)。顶层凸块(13)和内层迹线(11)形成为重叠在倒装芯片接合区域上。顶层凸块(13)的宽度形成得比内层迹线(11)的宽度宽。内层走线(11)的宽度比顶层凸块的宽度宽5〜20%。内层迹线(11)的宽度和顶层凸块(13)的宽度的相关性适用于具有至少两层的柔性印刷电路板。

著录项

  • 公开/公告号KR100779857B1

    专利类型

  • 公开/公告日2007-11-27

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20060031839

  • 申请日2006-04-07

  • 分类号H05K1/02;H01K1/18;

  • 国家 KR

  • 入库时间 2022-08-21 19:54:33

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