Wafer backside Metal layer routing method, structure of the same, chip package stacking method, and chip package stacking structure thereof

摘要

A structure for stacking a chip package is provided to avoid generation of a void trap by forming a metal interconnection in an etched recessed pattern by laser. A semiconductor chip is formed in a wafer(301). A plurality of recessed pattern parts are recessed in the backside of the wafer. A lower insulation layer(341) is formed on the backside of the wafer, positioned in a portion except the recessed pattern part in contact with a wafer in its adjacent layer. A passivation layer(311) is formed in the recessed part of the recessed pattern part, and metal is filled in the passivation layer. The recessed pattern part can be formed by an etch process using laser.