首页> 外国专利> device and method for managing transactions to read and write to eeprom memory or flash memory

device and method for managing transactions to read and write to eeprom memory or flash memory

机译:用于管理对eeprom存储器或闪存进行读写的事务的设备和方法

摘要

The present invention provides a data processing apparatus and method for processing transactions. The data processing apparatus has a non-volatile memory having a plurality of addresses at which data values can be stored, and a processor operable to process a transaction containing a sequence of update operations, each update operation identifying a target address in the non-volatile memory and a corresponding updated data value to be stored at that address. The processor is required to either complete the transaction in full or else disregard the entire transaction. The data processing apparatus further provides a volatile memory having a number of slots operable to temporarily store one or more updated data values, and mapping logic having a register associated with each slot, each register being programmable by the processor to identify an address range in the non-volatile memory to be mapped to the associated slot. The processor is operable when performing each update operation to ensure that one of the registers identifies an address range incorporating the target address for that update operation, such that when the target address is output to the mapping logic, the mapping logic will identify the relevant register having an address range that incorporates that target address and based thereon generate a remapped target address that causes the corresponding updated data value to be stored in the associated slot of the volatile memory rather than in the non-volatile memory. Any read addresses for read operations contained within the transaction are also routed via the mapping logic so that if they are seeking to access a data value that has already been updated, the address will be remapped to ensure that the updated data value is read from the volatile memory. Further, the processor is operable, upon detection of one or more predetermined events, to cause the updated data values in the volatile memory to be stored in the non-volatile memory at the associated target addresses. IMAGE IMAGE
机译:本发明提供了一种用于处理交易的数据处理设备和方法。该数据处理设备具有:非易失性存储器,其具有可存储数据值的多个地址;以及处理器,其可操作以处理包含一系列更新操作的事务,每个更新操作标识非易失性存储器中的目标地址。存储器和要存储在该地址的相应更新数据值。要求处理器要么完全完成交易,要么不理会整个交易。数据处理装置还提供了一种易失性存储器,其具有可操作以临时存储一个或多个更新的数据值的多个插槽,以及具有与每个插槽相关联的寄存器的映射逻辑,每个寄存器可由处理器编程以识别存储器中的地址范围。非易失性存储器要映射到关联的插槽。当执行每个更新操作时,处理器可操作以确保寄存器之一标识出包含该更新操作的目标地址的地址范围,从而当目标地址输出到映射逻辑时,映射逻辑将标识相关寄存器具有并入该目标地址的地址范围并且具有基于该目标地址的地址范围的地址而生成重新映射的目标地址,该目标地址导致将对应的更新数据值存储在易失性存储器的关联插槽中而不是非易失性存储器中。事务中包含的用于读取操作的任何读取地址也将通过映射逻辑进行路由,以便在它们试图访问已更新的数据值时,将重新映射该地址,以确保从内存中读取更新的数据值。易失性内存。此外,处理器在检测到一个或多个预定事件时可操作以使易失性存储器中的更新的数据值在相关联的目标地址处存储在非易失性存储器中。 <图像> <图像>

著录项

  • 公开/公告号DE60322387D1

    专利类型

  • 公开/公告日2008-09-04

    原文格式PDF

  • 申请/专利权人 ARM LTD.;

    申请/专利号DE20036022387T

  • 申请日2003-08-27

  • 分类号G06F12/02;G06F12/08;G06F12/0804;G07F7/10;G11C16/10;

  • 国家 DE

  • 入库时间 2022-08-21 19:47:36

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