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METHOD AND SYSTEM FOR CHIP DESIGN USING REMOTELY LOCATED RESOURCES

机译:利用远程定位资源进行芯片设计的方法和系统

摘要

PPROBLEM TO BE SOLVED: To provide a method and a system for chip design using remotely located resources. PSOLUTION: A multi-faceted design platform (104) acts as a tool for front-end hardware IC designers who design complex core base system on a chip. The design platform (104) uses a network to search and gain access to previously designed virtual core blocks. The design platform (104) provides a means to select (306) and transfer (308) all relevant information regarding the selected virtual core blocks and allows the designer to immediately incorporate the virtual core block into the new SoC design. The design platform (104) further generates the appropriate source core files (320) for immediate use with a plurality of known verification tools to verify both the integration and connectivity of the virtual core blocks as wel as the basic functions of the SoC design. PCOPYRIGHT: (C)2009,JPO&INPIT
机译:

要解决的问题:提供一种使用远程资源进行芯片设计的方法和系统。解决方案:多层面的设计平台(104)充当前端硬件IC设计人员的工具,他们在芯片上设计复杂的核心基础系统。设计平台(104)使用网络来搜索并获得对先前设计的虚拟核心块的访问。设计平台(104)提供一种选择(306)并传送(308)关于所选虚拟核心块的所有相关信息的手段,并且允许设计者立即将虚拟核心块并入新的SoC设计中。设计平台(104)还生成适当的源核心文件(320),以立即与多个已知的验证工具一起使用,以验证虚拟核心块的集成和连通性,如同SoC设计的基本功能一样。

版权:(C)2009,日本特许厅&INPIT

著录项

  • 公开/公告号JP2009104645A

    专利类型

  • 公开/公告日2009-05-14

    原文格式PDF

  • 申请/专利权人 CADENCE DESIGN SYSTEMS INC;

    申请/专利号JP20090022053

  • 发明设计人 ZIZZO CLAUDIO;

    申请日2009-02-02

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 19:44:38

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