首页> 外国专利> MULTI-CHIP PACKAGE REDUCING POWER-UP PEAK CURRENT

MULTI-CHIP PACKAGE REDUCING POWER-UP PEAK CURRENT

机译:多芯片封装,降低上电峰值电流

摘要

PROBLEM TO BE SOLVED: To provide a multi-chip package in which peak current during power-up is reduced.;SOLUTION: The multi-chip package includes a plurality of memory chips. Each of memory chip includes a memory cell array storing E-fuse data, a read-out control circuit performing read-out operation indicated by E-fuse data in response to a read signal, a first internal pad receiving a first signal, a read-out controller generating the read-out signal defining a read period for read-out operation in response to first control signal and generating a second control signal following the read period, and a second internal pad receiving the second control signal from the read-out controller. The plurality of memory chips are connected in series, the read-out control circuit and the read-out controller in each of a plurality of memory chips are operated so that the E-fuse data can be sequentially read across the plurality of memory chips.;COPYRIGHT: (C)2009,JPO&INPIT
机译:要解决的问题:提供一种多芯片封装,其中减小了上电期间的峰值电流。解决方案:多芯片封装包括多个存储芯片。每个存储芯片包括:存储E熔丝数据的存储单元阵列;响应于读取信号执行由E熔丝数据指示的读出操作的读出控制电路;接收第一信号的第一内部焊盘; -输出控制器响应于第一控制信号而产生定义用于读出操作的读出周期的读出信号,并在读出周期之后产生第二控制信号,以及第二内部焊盘从读出的信号中接收第二控制信号控制器。多个存储芯片被串联连接,多个存储芯片中的每一个中的读出控制电路和读出控制器被操作,使得可以在多个存储芯片上顺序地读取E熔丝数据。 ;版权:(C)2009,日本特许厅&INPIT

著录项

  • 公开/公告号JP2009026444A

    专利类型

  • 公开/公告日2009-02-05

    原文格式PDF

  • 申请/专利号JP20080187477

  • 发明设计人 KANG SANG-GU;

    申请日2008-07-18

  • 分类号G11C16/02;H01L25/04;H01L25/18;G11C16/06;

  • 国家 JP

  • 入库时间 2022-08-21 19:40:02

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