In the scan pass circuit which is loaded onto the logic circuit of test mannered null scan design mode

摘要

PROBLEM TO BE SOLVED: To determine the presence of a failure, and to specify a position thereof when the failure is found, in a short time, in a scan design test system of logic circuit 21 wherein a scan path circuit 23 is constituted by connecting serially flip-flops F1-F4 serving as an input and an output in a combinational logic circuit 22, and wherein test results therein are output serially in the flip-flops F1-F4 constituting the scan path circuit 23 to conduct a test easily.;SOLUTION: Selectors S2-S4 are provided to connect directly the inputs of the flip-flops F1-F4 constituting the scan path circuit 23 to an scan input D0, all the flip-flops F1-F4 are set once to the same value (1 or 0 in all), and are shift-output thereafter to specify a failure portion. A test period is brought into a clock number required for a shift operation for the number of steps + one step, even in the longest period.;COPYRIGHT: (C)2005,JPO&NCIPI