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Vertical NPN Transistor Fabricated in a CMOS Process With Improved Electrical Characteristics

机译:CMOS工艺制造的具有改善的电气特性的垂直NPN晶体管

摘要

A vertical NPN bipolar transistor includes a P-type semiconductor structure, an N-well as the collector, a P-Base region in the N-well and an N-type region as the emitter. The transistor further includes P-type region formed in the P-Base region and underneath the field oxide layer where the P-type region has a doping concentration higher than the P-base region. The P-type region functions to inhibit the lateral parasitic bipolar action so that the transistor action is confined to the intrinsic base region vertically underneath the emitter. In one embodiment, the P-type region is a boron field doping region. The boron field doping region can be the same field doping region used to form channel stops for NMOS transistors in a CMOS fabrication process.
机译:垂直NPN双极晶体管包括P型半导体结构,N阱作为集电极,N阱中的P基极区和N型区域作为发射极。该晶体管还包括形成在P基极区中并在场氧化层下方的P型区,其中P型区的掺杂浓度高于P基极区。 P型区域的作用是抑制横向寄生双极性作用,从而使晶体管的作用局限于发射极垂直下方的本征基极区域。在一个实施例中,P型区是硼场掺杂区。硼场掺杂区可以与用于在CMOS制造工艺中形成用于NMOS晶体管的沟道停止层的场掺杂区相同。

著录项

  • 公开/公告号US2009026578A1

    专利类型

  • 公开/公告日2009-01-29

    原文格式PDF

  • 申请/专利权人 SCHYI-YI WU;MARTIN ALTER;

    申请/专利号US20070829802

  • 发明设计人 SCHYI-YI WU;MARTIN ALTER;

    申请日2007-07-27

  • 分类号H01L29/732;H01L21/331;

  • 国家 US

  • 入库时间 2022-08-21 19:31:56

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