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Configuration and controlling method of fractional-N PLL having fractional frequency divider

机译:具有分数分频器的分数N分频PLL的配置和控制方法

摘要

The provided fractional frequency divider includes a divider controlling unit for generating a divider selection signal in response to a dual-edge triggering of an input signal and a frequency dividing unit coupled to the divider controlling unit for dividing the frequency of the input signal by one of an integer and a fractional dividers in response to the dual-edge triggering and the divider selection signal to generate the output signal of the fractional frequency divider. An operation of the frequency dividing unit is not suppressed when the integer divider is employed, the operation of the frequency dividing unit is not suppressed for a period of the input signal and is suppressed for half of that period, and this cycle is kept on recurring when the fractional divider is employed. The fractional-n PLL having the fractional frequency divider is also provided.
机译:所提供的分数分频器包括:分频器控制单元,用于响应于输入信号的双沿触发而产生分频器选择信号;以及分频单元,其耦合至分频器控制单元,用于将输入信号的频率除以下列之一:整数和分数分频器响应于双沿触发和分频器选择信号,以产生分数分频器的输出信号。当采用整数分频器时,不抑制分频单元的操作,在输入信号的一个周期内不抑制分频单元的操作,并且在该周期的一半内不抑制分频单元的操作,并且该循环不断重复进行。当使用分数除法器时。还提供了具有分数分频器的分数n PLL。

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