Fractional frequency divider PLL device and control method thereof

摘要

In the following B cycles, the second frequency-divided signal fA is maintained at a low level, while the third frequency-divided signal fB is maintained at a high level. The three-modulus prescaler 13 has a frequency division value (M−1) if the pseudo random values are negative values, and a frequency division value (M+1) if the pseudo random values are positive values, in accordance with the signs of the pseudo random values outputted from the ΣΔ modulator 8. After that, the frequency division value becomes M. A frequency division value of (MN+A+Bx) including the pseudo random value Bx is obtained in the comparison frequency divider 4. A fractional frequency division operation can be realized through ΣΔ modulation by using the pseudo random numbers including negative values, as they are.