首页> 外国专利> METHOD FOR FORMING A VERTICAL CHANNEL TRANSISTOR OF A SEMICONDUCTOR DEVICE, INCREASING THE WIDTH OF A WORD LINE HOLE THROUGH A WET CLEANING PROCESS USING BOE

METHOD FOR FORMING A VERTICAL CHANNEL TRANSISTOR OF A SEMICONDUCTOR DEVICE, INCREASING THE WIDTH OF A WORD LINE HOLE THROUGH A WET CLEANING PROCESS USING BOE

机译:通过BOE通过湿法清洗过程形成字线孔宽度的方法来形成半导体器件的垂直通道晶体管

摘要

PURPOSE: A method for forming a vertical channel transistor of a semiconductor device is provided to reduce the resistance of a word line by increasing the width of a word line hole through a wet cleaning process using BOE(Buffered Oxide Etchant).;CONSTITUTION: A word line hole(490) is formed by selectively etching an insulating layer reclaimed in a gap area between active pillars(410). The width of the word line hole is extended by etching the insulating layer isotropically. A residue generated in a process for forming the word line hole is removed. A conductive material is reclaimed in the word line hole.;COPYRIGHT KIPO 2010
机译:目的:提供一种用于形成半导体器件的垂直沟道晶体管的方法,以通过使用BOE(缓冲氧化物蚀刻剂)的湿法清洁工艺增加字线孔的宽度来减小字线的电阻。通过选择性地蚀刻在有源柱(410)之间的间隙区域中回收的绝缘层来形成字线孔(490)。通过各向同性地蚀刻绝缘层来扩展字线孔的宽度。去除在形成字线孔的过程中产生的残留物。在字线孔中回收导电材料。; COPYRIGHT KIPO 2010

著录项

  • 公开/公告号KR20090102166A

    专利类型

  • 公开/公告日2009-09-30

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20080027447

  • 发明设计人 KANG SANG KIL;

    申请日2008-03-25

  • 分类号H01L21/28;H01L21/336;H01L29/78;

  • 国家 KR

  • 入库时间 2022-08-21 19:12:31

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