6T FINFET CMOS SRAM CELL WITH AN INCREASED CELL RATIO

摘要

The invention two access devices - each access device comprised of a tri-gate transistor 400 having a single fin (fin) (410) - and the two pull-up device - each pull-up device has a single pin (410 ) a tri composed of a gate transistor (400) - and, two pull-down device - each pull-down device comprised of a tri-gate transistor 500 having a plurality of pins (410) - CMOS SRAM cell, including the relate to. Dual fin is also provided process for preparing a CMOS SRAM cell comprising a tri-gate transistor. Since the pin, the gate length is increased compared to a planar transistor having the same area. Therefore, without increasing the cell area on the supply voltage up to provide improved stability and increase the cell ratio and static noise margin.