6T FINFET CMOS SRAM CELL WITH AN INCREASED CELL RATIO

摘要

The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of tri-gate transistor (400) having a single fin (410); two pull up devices, each pull up device comprised of a tri-gate transistor (400) having a single fin (410); and two pull down devices, each pull down device comprised of a tri-gate transistor (500) having multiple fins(410). A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided. Due to the fins, the gate length is increased with respect to a planar transistor having the same area. Therefore, the cell ratio and static noise margin are increased, providing improved stability without increasing the cell area on the supply voltage.