Selecting optimal processor performance levels by using processor hardware feedback mechanisms adjusted according to stall count

摘要

A system is provided which uses hardware feedback to select optimal processor frequencies and reduce power consumption as part of adaptive power management. An effective P-state is determined in step 101 by comparing the cycle count of current actual processor frequency (APERF) adjusted by a cycle count of processor stall time with the cycle count of the maximum processor frequency available (MPERF). The target P-state is determined in block 103 by multiplying a measure of the percentage of time the processor is busy (%Busy) by the effective P-state. If the target P-state is not the same as the current P-state (step 105) the processor is transitioned to the new P-state in step 107 and the counters (APERF/MPERF) reset. The selection may also include a predetermined acceptable performance loss percentage.