Delaying the stop-clock signal of a chip by a set amount of time so that error handling and recovery can be performed before the clock is stopped

摘要

Disclosed is a method and circuit for operating self-checking logic 16, 18, 28 in a computer processing chip 10. The chip has functional units for detecting errors 28, for tracing the errors 18, and for controlling the processor clock 16, such that a clock-stop signal is generated by the self-checking logic which is used for error management and recovery. When a stop-clock signal is generated the signal is intercepted 440, a delay 445 is defined during which error-related, chip internal error handling and/ or recovery preparation actions are processed 470. At the end of the predetermined delay 460 the clock-stop action is performed 490, 495. A warning message to firmware may be sent to help in error and recovery management. The delay may be configured according to the location of the failure, the time needed to communicate with the stop-clock signal to the clock mechanism on the chip and/or the time needed to collect and store debug data.