Automatic clock adjustment circuit for IC(s) with D type flip=flops for data acceptance - synchronises data inputs to clock signal by delaying clock signal w.r.t. gate rise-fall and flip=flop transition-set times

摘要

The adjustment circuit has a D type flip-flop reset input connected to the output of a multiplexer (2) whose inputs receive clock signals delayed by a gate transition time. The flip-flop set output is connected to one input of an Exclusive-OR gate (3) whose second input receives data via a timing element (4) with delay equal to the sum of the set time and the flip-flop transition time. The Exclusive-OR output is connected to the input of a counter whose outputs are connected to the control inputs of a multiplexer. USE/ADVANTAGE - Automatic synchronising of clocking signals for IC with D type flip-flops for data acceptance.