METHOD AND SYSTEM FOR DESIGN RULE CHECKING ENHANCED WITH PATTERN MATCHING

摘要

PPROBLEM TO BE SOLVED: To enable circuit designers to waive certain design rules for their circuit designs. PSOLUTION: One embodiment of the invention includes receiving a first layout pattern containing a new layout of an integrated circuit pattern, a pattern matcher 110 processes the layout pattern and designates certain patterns of the integrated circuit pattern that meet design waiver information. The pattern matcher 110 generates a second layout pattern with the waived patterns marked. A design rule checker 115 subsequently processes the marked layout pattern and validates all but the marked patterns of the second layout pattern against a set of specified design rules. The design rule checker 115 generates a third layout pattern with only the unmarked patterns of the layout being validated against the set of specified design rules. PCOPYRIGHT: (C)2010,JPO&INPIT