Transferring data between system memory and input/output busses involves determining, via a request buffer, a memory-mapped, input/output (I/O) read request targeted for a first-in-first-out (FIFO) I/O device. The read request is targeted to a request address in a prefetchable memory space corresponding to the I/O device. It is determined whether the request address corresponds to an expected address in the prefetchable memory space. The expected address is determined based on one or more previous read requests targeted to the prefetchable memory space. The read request is reordered in the request buffer if the request address does not correspond to the expected address. The read request is fulfilled if the address corresponds to the expected address.
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