首页> 外国专利> Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions

Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions

机译:具有由线性形状的栅电极布局特征形成的栅电极导电结构的半导体器件部分,沿至少四个栅电极轨道定义,具有最小的端到端间距,并具有相应的非对称扩散区域

摘要

A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level region includes conductive features defined along at least four different virtual lines of extent in the first parallel direction.
机译:半导体器件包括衬底部分,该衬底部分具有相对于被定义为将衬底部分一分为二的虚拟线以非对称的方式在其中限定的多个扩散区域。半导体器件包括栅电极级区域,该栅电极级区域包括被限定为仅在第一平行方向上延伸的多个导电特征。由各自的原始布局特征制造多个在第一平行方向上具有共同的延伸线的导电特征中的相邻导电特征,所述各个原始布局特征通过端到端的间距彼此隔开,所述端到端的间距在整个导体上基本相等。栅电极水平区域,并被最小化到半导体器件制造能力所允许的程度。栅电极级区域包括沿第一平行方向上的至少四个不同的延伸虚拟线限定的导电特征。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号