Linear Gate Level Cross-Coupled Transistor Device with Connection Between Cross-Coupled Transistor Gate Electrodes Made Utilizing Interconnect Level Other than Gate Electrode Level

摘要

A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. The electrical connection between the gate electrodes of the first PMOS and second NMOS transistor devices is formed in part by one or more electrical conductors present within at least one interconnect level above the gate electrode level region.