首页> 外国专利> USE OF A BIASED PRECOAT FOR REDUCED FIRST WAFER DEFECTS IN HIGH-DENSITY PLASMA PROCESS

USE OF A BIASED PRECOAT FOR REDUCED FIRST WAFER DEFECTS IN HIGH-DENSITY PLASMA PROCESS

机译:使用偏光预涂来减少高密度等离子体工艺中的第一晶圆缺陷

摘要

According to various embodiments, the present teachings include methods for reducing first wafer defects in a high-density plasma chemical vapor deposition process. In an exemplary embodiment, the method can include running a deposition chamber for deposition of film on a first batch of silicon wafers and then cleaning interior surfaces of the deposition chamber. The method can further include inserting a protective electrostatic chuck cover (PEC) wafer on an electrostatic chuck in the deposition chamber and applying power to bias the PEC wafer while simultaneously precoating the deposition chamber with an oxide. The exemplary method can also include re-starting the deposition chamber for deposition of film on a second batch of silicon wafers.
机译:根据各种实施例,本教导包括用于在高密度等离子体化学气相沉积工艺中减少第一晶片缺陷的方法。在示例性实施例中,该方法可以包括运行沉积室以在第一批硅晶片上沉积膜,然后清洁沉积室的内表面。该方法可以进一步包括将保护性静电卡盘盖(PEC)晶片插入沉积室中的静电卡盘上,施加功率以偏置PEC晶片,同时用氧化物预涂覆沉积室。该示例性方法还可包括重新启动沉积室以在第二批硅晶片上沉积膜。

著录项

  • 公开/公告号US2010190352A1

    专利类型

  • 公开/公告日2010-07-29

    原文格式PDF

  • 申请/专利权人 RAJNEESH JAISWAL;

    申请/专利号US20090362320

  • 发明设计人 RAJNEESH JAISWAL;

    申请日2009-01-29

  • 分类号H01L21/31;B05D3/06;

  • 国家 US

  • 入库时间 2022-08-21 18:53:21

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