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Systems and methods for fabricating nanometric-scale semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks

机译:使用双应力氧化物/氮化物叠层制造具有双应力层的纳米级半导体器件的系统和方法

摘要

Systems and methods for fabricating semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks. A method comprises providing NMOS and PMOS regions, selectively forming a dual-stack tensile stress layer over the NMOS region by depositing a tensile silicon nitride layer over the NMOS and PMOS regions, depositing a tensile silicon oxide layer over the tensile silicon nitride layer, removing a portion of the tensile silicon oxide layer from the PMOS region, and removing a portion of the tensile silicon nitride layer from the NMOS region and selectively forming a dual stack compressive stress layer over the PMOS region by depositing a compressive silicon nitride layer over the NMOS and PMOS regions, depositing a compressive silicon oxide layer over the compressive silicon nitride layer, removing a portion of the compressive silicon oxide layer from the NMOS region, and removing a portion of the compressive silicon nitride layer from the NMOS region.
机译:使用双应力氧化物/氮化物叠层制造具有双应力层的半导体器件的系统和方法。一种方法包括提供NMOS和PMOS区域,通过在NMOS和PMOS区域上方沉积拉伸的氮化硅层,在NMOS区域上方选择性地形成双堆叠拉伸应力层,在拉伸的氮化硅层上方沉积拉伸的氧化硅层,去除从PMOS区域中去除一部分拉伸氧化硅层,并从NMOS区域中去除一部分拉伸氮化硅层,并通过在NMOS之上沉积压缩氮化硅层,在PMOS区域之上选择性地形成双叠层压缩应力层。在PMOS区域和PMOS区域中,在压缩性氮化硅层上方沉积压缩性氧化硅层,从NMOS区域去除压缩性氧化硅层的一部分,并且从NMOS区域去除压缩性氮化硅层的一部分。

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