Substrate processing system for setting uniform module cycle length and access control time lag in two pipeline processing systems

摘要

In a substrate processing system according to the present invention, module cycle periods at a plurality of process modules PM₁ through PM₄ connected around a transfer module TM having installed therein a vacuum pressure-side transfer robot RB₁, each representing the sum of a wafer stay time including the wafer processing time and an attendant busy time during which the wafer is transferred before and after the wafer stay time, are all set to a uniform length. The vacuum pressure-side transfer robot RB₁ takes out a processed wafer W_i and carries a next wafer W_i+1 to be processed next by executing a pick and place operation for each of the process modules PM₁ through PM₄ during a single access to the process module.