A SEMICONDUCTOR DEVICE INCLUDING STRESS RELAXATION GAPS FOR ENHANCING CHIP PACKAGE INTERACTION STABILITY

摘要

By dividing a single chip area into individual sub areas (200a, 200b, 200c on the basis of one or more stress relaxation regions 280a, 280b,) a thermally- induced stress in each of the sub areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip (200) may be used compared to conventional strategies.