SEMICONDUCTOR MEMORY DEVICE WHICH HAS A HIERARCHICAL BIT-LINE STRUCTURE OF SUCCESSIVELY AMPLIFYING DATA OF ADJACENT GLOBAL BIT-LINES

摘要

PURPOSE: A semiconductor memory device is provided to increase voltage difference between global bit-line pairs by minimizing the influence of coupling noise due to the coupling capacitance.;CONSTITUTION: A memory cell array comprises a plurality of first memory cells connected between word lines and first local bit lines, and a plurality of second memory cells connected between the word lines and second local bit lines. A switching block connects the first local bit lines to the first global bit lines during a first sensing period(ST1) at read operation. The switching block interlinks the second local bit lines to second global bit lines during a second sensing period. The sensing block amplifies data of the first global bit lines during the first sensing period. The sensing block amplifies data of the second global bit lines during the second sensing period.;COPYRIGHT KIPO 2010