首页> 外国专利> TRANSISTOR AND THE MANUFACTURING METHOD THEREOF FOR IN ADVANCE PREVENTING THE SHORT PHENOMENON THAT IT IS BURIED WITH THE METAL MATERIAL AND VOID CAN GENERATE

TRANSISTOR AND THE MANUFACTURING METHOD THEREOF FOR IN ADVANCE PREVENTING THE SHORT PHENOMENON THAT IT IS BURIED WITH THE METAL MATERIAL AND VOID CAN GENERATE

机译:晶体管及其制造方法可预先防止金属材料渗入空洞而产生短时现象

摘要

PURPOSE: It improves the profile of the gate electrode and transistor and manufacturing method thereof improve the gap fill performance of the interlayer insulating film formed on the top. The generation of the void is prevented.;CONSTITUTION: A layer of conductive material(105) is formed on the semiconductor substrate(101). A lattice damage layer(107) damaging lattice is formed about a part thickness of the layer of conductive material. The gate electrode having the level difference in the lattice damage layer and side the layer of conductive material is patterned is formed. The source/drain is formed based on the gate electrode within the semiconductor substrate of the either side.;COPYRIGHT KIPO 2010
机译:目的:改善栅电极和晶体管的轮廓,其制造方法改善形成在顶部的层间绝缘膜的间隙填充性能。防止产生空隙。组成:在半导体衬底(101)上形成一层导电材料(105)。在导电材料层的一部分厚度周围形成破坏晶格的晶格损坏层(107)。形成在晶格损伤层中和在对导电材料层进行图案化的一侧具有水平差的栅电极。源/漏基于两侧半导体衬底内的栅电极形成。; COPYRIGHT KIPO 2010

著录项

  • 公开/公告号KR20100079155A

    专利类型

  • 公开/公告日2010-07-08

    原文格式PDF

  • 申请/专利权人 DONGBU HITEK CO. LTD.;

    申请/专利号KR20080137570

  • 发明设计人 CHOI YONG KEON;

    申请日2008-12-30

  • 分类号H01L21/336;H01L29/78;

  • 国家 KR

  • 入库时间 2022-08-21 18:32:18

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