首页> 外国专利> BIASED, TRIPLE-WELL FULLY DEPLETED SOI STRUCTURE, AND VARIOUS METHODS OF MAKING AND OPERATING SAME

BIASED, TRIPLE-WELL FULLY DEPLETED SOI STRUCTURE, AND VARIOUS METHODS OF MAKING AND OPERATING SAME

机译:偏置的,三井全耗尽的SOI结构以及相同的制造和操作方法

摘要

in accordance with one embodiment of the invention the device is a bulk substrate (30A), insulating buried layer (30B), and an active layer (30C) containing a silicon-on-insulator and comprises a substrate 30 formed on the transistor 32, the bulk substrate (30A) has a first dopant material is doped first well 50 is formed and, the first well (50) has a second dopant material of opposite type of the first dopant material is doped. The apparatus further comprises a second well (52) formed in the first well (50) of said bulk substrate (30A), the transistor 32 is formed on the active layer (30C) of the upper part of the second well (52) and, also the device further comprises electrical contacts 62 for the electrical contact 60 and the second well 52 for the first well (50). According to one embodiment of the invention, the bulk substrate (30A), the oxide buried layer (30B) and the active layer (30C) containing a silicon-on-insulator substrate 30 is provided a method of forming a transistor (32) formed on and , the bulk substrate (30A) is doped with the first dopant material. The method includes forming a first well 50 in the bulk substrate (30A) by performing a first ion implant process using a dopant material of a second type opposite the first dopant material, the first dopant material and using the dopant material of the same type by performing a second ion implantation process to form a second well (52) in the first well 50 in the bulk substrate (30A), said second well (52) the top of the active layer forming a transistor (32) to (30C), and the conductive contacts 60 formed in the first well (50) and forming a conductive contact (62) in the second well (52). The method further comprising the step of forming the source / drain regions, the method comprising a contact well (58) formed in said first well (50) of said bulk substrate (30A), said contact well (58 ) is composed of the second dopant material and the dopant material of the same type and concentration of dopant material of the contact well 58 is higher than the concentration of dopant material in said first well (50).
机译:根据本发明的一个实施例,该器件是块状衬底(30A),绝缘掩埋层(30B)和包含绝缘体上硅的有源层(30C),并且包括形成在晶体管32上的衬底30,体衬底(30A)具有第一掺杂剂材料被掺杂,形成第一阱50,并且第一阱(50​​)具有与第一掺杂剂材料相反类型的第二掺杂剂材料。该设备还包括形成在所述块状衬底(30A)的第一阱(50​​)中的第二阱(52),晶体管32形成在第二阱(52)的上部的有源层(30C)上,并且该装置还包括用于电触点60的电触点62和用于第一阱50的第二阱52。根据本发明的一个实施例,提供了一种包含绝缘体上硅衬底30的体衬底(30A),氧化物掩埋层(30B)和有源层(30C),该方法形成了形成的晶体管(32)。然后,在体衬底(30A)中掺杂有第一掺杂剂材料。该方法包括通过使用与第一掺杂剂材料相对的第二类型的掺杂剂材料,通过第一掺杂剂材料执行第二离子注入工艺以及通过使用相同类型的掺杂剂材料来执行第一离子注入工艺,从而在块状衬底(30A)中形成第一阱50。进行第二离子注入工艺以在块状衬底(30A)中的第一阱50中形成第二阱(52),所述第二阱(52)在有源层的顶部形成晶体管(32)至(30C),导电触点60形成在第一阱50中,导电触点62形成在第二阱52中。该方法还包括形成源/漏区的步骤,该方法包括在所述块状衬底(30A)的所述第一阱(50​​)中形成的接触阱(58),所述接触阱(58)由第二衬底构成。掺杂材料和接触阱58的相同类型的掺杂材料和浓度的掺杂材料高于所述第一阱(50​​)中的掺杂材料的浓度。

著录项

  • 公开/公告号KR100939094B1

    专利类型

  • 公开/公告日2010-01-28

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20047014856

  • 申请日2002-12-17

  • 分类号H01L29/786;H01L23/58;

  • 国家 KR

  • 入库时间 2022-08-21 18:31:34

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