首页> 外国专利> A process for the preparation of a gate electrodes structure, with an increase of the integrity of a gate stack with a large ε by means of protecting a coating on the gate under side during the outer surface of the gate side

A process for the preparation of a gate electrodes structure, with an increase of the integrity of a gate stack with a large ε by means of protecting a coating on the gate under side during the outer surface of the gate side

机译:通过在栅极侧的外表面期间保护栅极下侧上的涂层来制备具有大ε的栅极堆叠的完整性的栅电极结构的制备方法

摘要

Complex gate stack with a dielectric material with a large ε and a metal-containing electrode material are formed by a protective layer, for example a silicon nitride layer, which during the entire production sequence, on the underside of the gate stack is maintained. For this purpose, a mask material before the removal of the deck materials on the spacer layer is applied which, for the encapsulation of the gate stack during the selective epitaxial growth of a deformation induzier ends semiconductor alloy be used. Consequently, it is possible for a better integrity over the entire production sequence, to be maintained, while at the same time, one or more lithographic processes are avoided.
机译:由具有大的ε的介电材料和含金属的电极材料的复合栅叠层由保护层例如氮化硅层形成,该保护层在整个生产过程中保持在栅叠层的下侧上。为此目的,在去除间隔层上的平台材料之前,施加掩模材料,该掩模材料用于在变形工业端的选择性外延生长期间封闭半导体叠层以封闭半导体叠层。因此,有可能在整个生产过程中保持更好的完整性,同时避免一种或多种光刻工艺。

著录项

  • 公开/公告号DE102008059647B3

    专利类型

  • 公开/公告日2010-06-10

    原文格式PDF

  • 申请/专利权人

    申请/专利号DE20081059647

  • 发明设计人

    申请日2008-11-28

  • 分类号H01L21/336;H01L21/8234;H01L21/28;

  • 国家 DE

  • 入库时间 2022-08-21 18:28:39

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