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Semiconductor equipment and semiconductor mask layout

机译:半导体设备和半导体掩膜版图

摘要

PROBLEM TO BE SOLVED: To prevent increase of contact resistance in a contact of high aspect ratio in a high-density semiconductor device.;SOLUTION: This semiconductor device comprises a plurality of semiconductor regions (201, 204) separated by an element isolation region, at least one interlayer insulating film formed on the plurality of semiconductor regions, a plurality of wiring layers formed on the interlayer insulating film, and a plurality of contacts (203, 205) arranged in the interlayer insulating film to electrically connect the plurality of semiconductor regions and the plurality of wiring layers. The plurality of contacts comprise a first group of contacts (205) whose distance to the closest adjoining contact is no less than 3 μm, and a second group of contacts (203) whose distance to the closest adjoining contact is less than 3 μm. The diameter of the contact hole of the first group of contacts is greater than that of the second group of contacts. The foregoing are the main features of this invention.;COPYRIGHT: (C)2008,JPO&INPIT
机译:解决的问题:在高密度半导体器件中,为了防止高纵横比的接触中的接触电阻增大。解决方案:该半导体器件包括多个由元件隔离区隔开的半导体区(201、204),至少一个形成在所述多个半导体区域上的层间绝缘膜,形成在所述层间绝缘膜上的多个布线层以及布置在所述层间绝缘膜中以电连接所述多个半导体区域的多个触点(203、205)多个配线层。多个触头包括第一组触头(205),其到最接近的相邻触头的距离不小于3μm,第二组触头(203),其到最接近的相邻触头的距离小于3μm。 ; m。第一组触头的接触孔直径大于第二组触头的直径。前述是本发明的主要特征。版权所有:(C)2008,日本特许厅

著录项

  • 公开/公告号JP4809319B2

    专利类型

  • 公开/公告日2011-11-09

    原文格式PDF

  • 申请/专利权人 パナソニック株式会社;

    申请/专利号JP20070302783

  • 发明设计人 立岩 健二;

    申请日2007-11-22

  • 分类号H01L21/82;H01L21/822;H01L27/04;H01L23/52;H01L21/3205;H01L21/768;

  • 国家 JP

  • 入库时间 2022-08-21 18:19:58

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