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Controlling Select Gate Voltage During Erase To Improve Endurance In Non-Volatile Memory
Controlling Select Gate Voltage During Erase To Improve Endurance In Non-Volatile Memory
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机译:在擦除过程中控制选择的栅极电压以提高非易失性存储器的耐久性
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摘要
A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage.
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