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Testing method for a semiconductor integrated circuit device, semiconductor integrated circuit device and testing system

机译:半导体集成电路器件的测试方法,半导体集成电路器件和测试系统

摘要

A method that divides semiconductor integrated circuit devices (corresponding to S1 and S2) into a plurality of groups and tests them simultaneously has the semiconductor integrated circuit devices operate with a clock signal (corresponding to CLK1 and CLK2) having a frequency different from that in other groups in at least one group. A test is performed without decreasing the number of chips tested at one time.
机译:将半导体集成电路器件(对应于S 1 和S 2 )分为多个组并同时测试它们的方法是使半导体集成电路器件带有时钟工作至少一组中具有与其他组不同的频率的信号(对应于CLK 1 和CLK 2 )。执行测试时不会减少一次测试的芯片数。

著录项

  • 公开/公告号US2010315116A1

    专利类型

  • 公开/公告日2010-12-16

    原文格式PDF

  • 申请/专利权人 SHUNICHI SEYA;

    申请/专利号US20100801210

  • 发明设计人 SHUNICHI SEYA;

    申请日2010-05-27

  • 分类号G01R31/26;

  • 国家 US

  • 入库时间 2022-08-21 18:15:04

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