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Preventing access to stub traces on an integrated circuit package

机译:防止访问集成电路封装上的存根轨迹

摘要

An integrated circuit (IC) package includes a printed circuit board (PCB) substrate and a plurality of package attachment terminals. The package attachment terminals are used to conduct electrical signals from a die that is attached and bonded onto the PCB substrate. The PCB substrate has a side edge and includes a plurality of electrically-conductive paths. Each one of the plurality of paths includes an electroplated bond pad, a trace, and a stub trace. The die is connected to the bond pad and the trace couples the bond pad to a respective one of the package attachment terminals. The stub trace is used to facilitate the electroplating process. The stub trace extends from the trace and terminates at a distance away from the side edge. The stub trace is not visible from the side of the IC package and therefore prevents access to IC buses on the package.
机译:集成电路(IC)封装包括印刷电路板(PCB)基板和多个封装附接端子。封装连接端子用于传导来自管芯的电信号,该管芯连接并键合到PCB基板上。 PCB基板具有侧边缘并且包括多个导电路径。多个路径中的每一个都包括电镀键合焊盘,迹线和短线迹线。管芯连接到焊盘,并且迹线将焊盘耦合到封装附接端子中的相应一个。存根迹线用于促进电镀过程。存根轨迹从轨迹延伸,并终止于离侧边缘一定距离的地方。存根跟踪从IC封装的侧面不可见,因此阻止访问封装上的IC总线。

著录项

  • 公开/公告号US8049324B1

    专利类型

  • 公开/公告日2011-11-01

    原文格式PDF

  • 申请/专利权人 RUBEN C. ZETA;

    申请/专利号US20070800304

  • 发明设计人 RUBEN C. ZETA;

    申请日2007-05-03

  • 分类号H01L23/48;H01L23/04;

  • 国家 US

  • 入库时间 2022-08-21 18:10:47

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