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Automated method for buffering in a VLSI design

机译:在VLSI设计中用于缓冲的自动化方法

摘要

Buffers are placed on selected nets coupled to input and output pins of entities in an IC device. This includes loading selected input and output pins of entities prior to respectively buffering nets of the entities and buffering in successive iterations, which includes setting artificial loads on selected input pins. The buffering in a current iteration is limited to i) buffering nets on the current iteration entity for receivers on the current iteration entity and ii) buffering nets on the current iteration entity directly coupled to respective nets of an immediately adjacent entity that has been buffered already in a preceding one of iterations, but only if the already buffered net is coupled to a receiver on its own net or a receiver on some other already buffered net via nets that have all been buffered via one or more of the preceding iterations.
机译:缓冲区放置在选定的网络上,该网络耦合到IC器件中实体的输入和输出引脚。这包括在分别缓冲实体的网之前加载实体的选定输入和输出引脚,以及在连续迭代中进行缓冲,这包括在选定的输入引脚上设置人工负载。当前迭代中的缓冲仅限于:i)当前迭代实体上的缓冲网,用于当前迭代实体上的接收器;以及ii)当前迭代实体上的缓冲网,直接耦合到已经缓冲的直接相邻实体的各个网络。但是,仅当已经缓冲的网络通过本身已经通过一个或多个先前迭代进行缓冲的网络耦合到其自己的网络上的接收器或耦合到某个其他已经缓冲的网络上的接收器时,才可以。

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